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ZL30406 SONET/SDH Clock Multiplier PLL
Data Sheet Features
* * * * Meets jitter requirements of Telcordia GR-253CORE for OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 77.76 MHz Provides a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Provides enable/disable control of output clocks Accepts a CMOS reference at 19.44 MHz 3.3 V supply
ZL30406QGC ZL30406QGG1
March 2006
Ordering Information
64 Pin TQFP Trays 64 Pin TQFP* Trays, Bake & Drypack *Pb Free Matte Tin
-40C to +85C
Description
The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30406 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-16, STM-4 and STM-1 rates. The ZL30406 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 77.76 MHz, a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled.
* * * *
Applications
* * SONET/SDH line cards Network Element timing cards
LPF
C77oEN-A C77oEN-B OC-CLKoEN
C77o,C155o C19o, C38o, CML-P/N outputs
OC-CLKoP/N C19i Frequency & Phase Detector 19.44MHz C77oP/N-D BIAS
Reference & Bias circuit
Loop Filter
Output
VCO
C77oP/N-A C77oP/N-B C77oP/N-C
Interface Circuit
C19o
VDD GND
VCC
FS1-2
C19oEN C77oEN-C C77oEN-D 15
Figure 1 - Functional Block Diagram
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Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30406
Data Sheet
GND VCC1 VCC OC-CLKoN OC-CLKoP GND VCC2 LPF GND GND BIAS OC-CLKoEN C77oEN-A C77oEN-B C77oEN-C C77oEN-D
GND C77oN-A C77oP-A VCC GND C77oP-B C77oN-B VCC GND C77oN-C C77oP-C VCC GND C77oP-D C77oN-D VCC 64
2
62
60
58
56
54
52
50
48 46 44
65 - EP_GND
4 6
42 8 10 38 12 36 14 34 16 18 20 22 24 26 28 30 32
ZL30406
40
GND VCC VDD GND VCC GND VDD GND NC GND GND NC GND C19o VDD GND
Figure 2 - TQFP 64 pin (Top View)
Change Summary
The following table captures the changes from the February 2005 issue. Page 1 Item Change Updated Ordering Information.
Pin Description
Pin Description Table Pin # 1 2 3 4 5 6 7 Name GND VCC1 VCC OC-CLKoN OC-CLKoP GND VCC2 Ground. 0 volt. Positive Analog Power Supply. +3.3 V 10% Positive Analog Power Supply. +3.3 V 10% SONET/SDH Clock (CML Output). These outputs provide a programmable differential CML clock at 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz. The output frequency is selected with FS2 and FS1 pins. Ground. 0 volt Positive Analog Power Supply. +3.3 V 10% Description
GND VDD NC NC NC VDD IC FS2 FS1 C19oEN GND C19i VDD GND NC GND
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Pin Description Table (continued) Pin # 8 9 10 11 12 Name LPF GND GND BIAS OC-CLKoEN Description
Data Sheet
Low Pass Filter (Analog). Connect to this pin external RC network (RF and CF) for the low pass filter. Ground. 0 volt Ground. 0 volt Bias. See Figure 11 for the recommended bias circuit. SONET/SDH Clock Enable (CMOS Input). If tied high this control pin enables the OC-CLKoP/N differential driver. Pulling this input low disables the output clock without deactivating differential drivers. C77 Clock Output Enable A (CMOS Input). If tied high this control pin enables the C77oP/N-A output clock. Pulling this input low disables the output clock without deactivating differential drivers. C77 Clock Output Enable B (CMOS Input). If tied high this control pin enables the C77oP/N-B output clock. Pulling this input low disables the output clock without deactivating differential drivers. C77 Clock Output Enable C (CMOS Input). If tied high this control pin enables the C77oP/N-C output clock. Pulling this input low disables the output clock without deactivating differential drivers. C77 Clock Output Enable D (CMOS Input). If tied high this control pin enables the C77oP/N-D output clock. Pulling this input low disables the output clock without deactivating differential drivers. Ground. 0 volt Positive Digital Power Supply. +3.3 V 10% No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Positive Digital Power Supply. +3.3 V 10% Internal Connection. Connect this pin to Ground (GND). Frequency Select 2-1 (CMOS Input). These inputs program the clock frequency on the OC-CLKo output. The possible output frequencies are 19.44 MHz (00), 38.88 MHz (01), 77.76 MHz (10), 155.52 MHz (11). C19o Output Enable (CMOS Input). If tied high this control pin enables the C19o output clock. Pulling this pin low forces output driver into a high impedance state. Ground. 0 volt C19 Reference Input (CMOS Input). This pin is a single-ended input reference source used for synchronization. This pin accepts 19.44 MHz. Positive Digital Power Supply. +3.3 V 10% Ground. 0 volt No internal bonding Connection. Leave unconnected. Ground. 0 volt.
C77oEN-A 13 C77oEN-B 14 C77oEN-C 15 C77oEN-D 16 17 18 19 20 21 22 23 24 25 26 GND VDD NC NC NC VDD IC FS2 FS1 C19oEN
27 28 29 30 31 32
GND C19i VDD GND NC GND
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Pin Description Table (continued) Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Name GND VDD C19o GND NC GND GND NC GND VDD GND VCC GND VDD VCC GND VCC C77oN-D C77oP-D GND VCC C77oP-C C77oN-C GND VCC C77oN-B C77oP-B GND VCC C77oP-A C77oN-A GND EP_GND Ground. 0 volt Positive Digital Power Supply. +3.3 V 10% Description
Data Sheet
C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS clock at 19.44 MHz. Ground. 0 volt No internal bonding Connection. Leave unconnected. Ground. 0 volt Ground. 0 volt No internal bonding Connection. Leave unconnected. Ground. 0 volt Positive Digital Power Supply. +3.3 V 10% Ground. 0 volt Positive Analog Power Supply. +3.3 V 10% Ground. 0 volt Positive Digital Power Supply. +3.3 V 10% Positive Analog Power Supply. +3.3 V 10% Ground. 0 volt Positive Analog Power Supply. +3.3 V 10%. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt Positive Analog Power Supply. +3.3 V 10%. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt Positive Analog Power Supply. +3.3 V 10%. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt Positive Analog Power Supply. +3.3 V 10%. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt Exposed die Pad Ground. 0 volt (connect to GND)
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1.0 Functional Description
Data Sheet
The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and a brief description is presented in the following sections.
1.1
Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit and averaged to control the VCO frequency.
1.2
Loop Filter
The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as shown below.
ZL30406
LPF Internal Loop Filter RF CF
RF=8.2 k, CF=470 nF (for 14 kHz PLL bandwidth)
Figure 3 - External Loop Filter
1.3
VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal, generates a primary frequency. The VCO output is connected to the Output Interface Circuit that divides VCO frequency and buffers generated clocks.
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1.4 Output Interface Circuit
Data Sheet
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at 77.76 MHz, one programmable CML differential clock (19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz) controlled with FS1-2 pins and a single-ended 19.44 MHz output clock. This block provides also a 19.44 MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable pin.
Output Clocks C77oP/N-A C77oP/N-B C77oP/N-C C77oP/N-D OC-CLKoP/N C19o
Output Enable Pins C77oEN-A C77oEN-B C77oEN-C C77oEN-D OC-CLKoEN C19oEN
Table 1 - Output Enable Control To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations. The output clock frequency of the OC-CLKo CML differential output clock is selected with FS1-2 pins as shown in the following table. FS2 0 0 1 1 FS1 0 1 0 1 OC-CLKo Frequency 19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz
Table 2 - OC-CLKo Clock Frequency Selection
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2.0
2.1
Data Sheet
Applications
Ultra-Low Jitter SONET/SDH Equipment Clocks
The ZL30406 functionality and performance complements the entire family of the Zarlink's advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating at OC-48/STM-16 rate (2.5 Gbit/s). The ZL30406 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 4).
C19i
ZL30406
OC-CLKo C77oA C77oB C77oC C77oD C19o
C77oEN-D
CML LVPECL LVPECL LVPECL LVPECL CMOS
LPF
OC-CLKoEN C77oEN-B C77oEN-A C19oEN
RF CF
155.52 MHz, 77.76 MHz 38.88 MHz, 19.44 MHz 77.76 MHz 77.76 MHz 77.76 MHz 77.76 MHz 19.44 MHz
C77oEN-C
PRI SEC Synchronization Reference Clocks RefSel RefAlign PRIOR SECOR LOCK HOLDOVER
MT90401 or ZL30407
C19o C155o C34o/C44o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o
CMOS LVDS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
19.44 MHz 155.52 MHz 34.368 MHz or 44.736 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz
C20i
R/W A0 - A6
20 MHz OCXO
D0 - D7
DS CS
Data Port
uP
Controller Port
Note: Only main functional connections are shown
Figure 4 - SONET/SDH Equipment Timing Card
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Data Sheet
The ZL30406 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 5).
C19i
ZL30406
LPF
C77oEN-A C77oEN-B C77oEN-C
OC-CLKo C77oA C77oB C77oC C77oD C19o
CML LVPECL LVPECL LVPECL LVPECL CMOS
155.52 MHz, 77.76 MHz 38.88 MHz, 19.44 MHz 77.76 MHz 77.76 MHz 77.76 MHz 77.76 MHz 19.44 MHz
C1
C2
C19oEN
R1
C77oEN-D
R1 = 680 C1 = 820 nF C2 = 22 nF
OC-CLKoEN
PRI SEC Synchronization Reference Clocks RSEL
MT9046
LOCK HOLDOVER C20i 20 MHz TCXO
MS1 MS2 FS1 FS2
C19o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
19.44 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz
FLOCK PCCi TCLR
uC
Hardware Control
Note: Only main functional connections are shown
Figure 5 - SONET/SDH Line Card
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2.2 2.2.1 Recommended Interface Circuit LVPECL to LVPECL Interface
Data Sheet
The C77oP/N-A, C77oP/N-B, C77oP/N-B, and C77oP/N-D outputs provide differential LVPECL clocks at 77.76 MHz. The LVPECL output drivers require a 50 termination connected to the VCC-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed as close as possible to the LVPECL receiver.
+3.3 V
0.1 uF ZL30406 VCC VCC=+3.3 V LVPECL Receiver
LVPECL Driver
C77oP-A
Z=50 Z=50
R1
R1
C77oN-A R2 GND Typical resistor values: R1 = 130 , R2 =82 R2
Figure 6 - LVPECL to LVPECL Interface
2.2.2
CML to CML Interface
The CMLP/N output provides a differential CML/LVDS compatible clock at 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz selected with FS1-2 pins. The output drivers require a 50 load at the terminating end if the receiver is CML type.
+3.3 V Low Impedance DC bias source CML Receiver
0.1 uF ZL30406 VCC
CML Driver
0.1 uF OC-CLKoP
Z=50 Z=50
50
50
OC-CLKoN 0.1 uF GND
Figure 7 - CML to CML Interface
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2.2.3 CML to LVDS Interface
Data Sheet
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage) as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for LVDS applications.
+3.3 V
0.1 uF ZL30406 VCC 10 nF VCC=+3.3 V LVDS Receiver
CML Driver
OC-CLKoP
Z=50 Z=50
R1
R1
100
OC-CLKoN 10 nF R2 GND R2
Typical resistor values: R1 = 16 k, R2 = 10 k
Figure 8 - LVDS Termination
2.2.4
CML to LVPECL Interface
In the case when more than four 77.76 MHz clocks are required to drive LVPECL receivers then the unused OCCLKo clock (CML output) can be configured to output the 77.76 MHz clock and interface to the LVPECL receiver as is shown in the Figure 9. The terminating resistors should be placed as close as possible to the LVPECL receiver.
+3.3 V
0.1 uF VCC ZL30406 10 nF VCC=+3.3 V LVPECL Receiver
CML Driver
OC-CLKoP 77.76MHz OC-CLKoN
Z=50 Z=50
R1
R1
10 nF R2 GND Typical resistor values: R1 = 82 , R2 =130 R2
Figure 9 - CML to LVPECL Interface
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2.3 Tristating LVPECL Outputs
Data Sheet
The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V. For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling capacitors can be used as shown in Figure 10. Typically this might be required in hot swappable applications. Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC coupling capacitors. During disable mode (C77oEN pin pulled low) those capacitors present infinite impedance to the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6 are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4, R5 and R6 should not be populated.
C77oEN ZL30406 C1 0.1 u
3.3 V 3.3 V R3 127 Z=50 R5 127
Z=50 C2 0.1 u
R1 200
R2 200
R4 82.5
R6 82.5
Figure 10 - Tristatable LVPECL Outputs
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2.4 Power Supply and BIAS Circuit Filtering Recommendations
Data Sheet
Figure 11 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink's web site for updates.
0.1 uF +3.3 V Power Rail GND GND VCC
0.1uF GND VCC
0.1uF GND VCC
0.1uF VCC
0.1uF
Ferrite Bead + 0.1 uF 10 uF 0.1 uF
4.7 + 33 uF
GND 64 VCC1 2 VCC 0.1 uF VCC2 + 33 uF 0.1 uF BIAS + 33 uF 0.1 uF 4 6 GND 8 GND 10GND 11 12 14 16 18 GND VDD
0.1 uF 62 60 58 56 54 52 50 48 GND VCC VDD 0.1 uF VCC 0.1 uF VDD 0.1 uF
ZL30406
220
46 GND 44 GND 42 GND 40 GND GND38 GND36 34
VDD GND 0.1 uF
20
22 VDD
24
26 GND
28 VDD
30 GND
32 GND 0.1uF
0.1uF
0.1uF
Notes: 1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same 2. Select Ferrite Bead with IDC > 400mA and R DC in a range from 0.10 to 0.15
Figure 11 - Power Supply and BIAS circuit filtering
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3.0 Characteristics
Characteristics 1 2 3 4 5 6 Supply voltage Voltage on any pin Current on any pin ESD Rating Storage temperature Package power dissipation Sym VDDR, VCCR VPIN IPIN VESD TST PPD -55 Min. TBD -0.5 -0.5 Max. TBD VCC + 0.5 VDD + 0.5 30 1500 125 1.8 Absolute Maximum Ratings
Data Sheet
Units V V mA V C W
Voltages are with respect to ground unless otherwise stated. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics 1 2 Operating Temperature Positive Supply Sym. TOP VDD, VCC VCC_VCO Min. -40 3.0 Typ. 25 3.3 Max. +85 3.6 Units C V Notes
Voltages are with respect to ground unless otherwise stated. Typical figures are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics Characteristics 1 Supply Current Sym. IDD+ICC Min. Typ. 140 Max. 155 Units mA Notes LVPECL, CML drivers disabled and unterminated Note 1,2
2
Incremental Supply Current to single LVPECL driver (driver enabled and terminated, see Figure 6) Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 7) CMOS: High-level input voltage CMOS: Low-level input voltage CMOS: Input leakage current, C19i
ILVPECL
40
mA
3
ICML
24
mA
Note 3
4 5 6
VIH VIL IIL
0.7VDD 0 1
VDD 0.3VDD
V V uA VI = VDD or 0V
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DC Electrical Characteristics (continued) Characteristics 7 CMOS: Input bias current for pulled-down inputs: FS1, FS2, C77oEN-A, C77oEN-C, C77oEN-D, OC-CLKoEN CMOS: Input bias current for pulled-up inputs: , C77oEN-B, C19o_EN CMOS: High-level output voltage CMOS: Low-level output voltage CMOS: C19o output rise time (18pF) CMOS: C19o output fall time (18pF) LVPECL: Differential output voltage LVPECL: Offset voltage LVPECL: Output rise/fall times CML: Differential output voltage CML: Offset voltage (Also referred to as common mode voltage) CML: Output rise/fall times Sym. IB-PU Min. Typ. 300 Max. Units uA
Data Sheet
Notes VI = VDD
8
IB-PD
90
uA
VI = 0V
9 10 11 12 13 14 15 16 17
VOH VOL TR TF IVOD_LVPECLI VOS_LVPECL TRF IVOD_CMLI VOS_CML
2.4 0.4 1.8 1.1 1.30 Vcc1.38 Vcc1.27 260 0.70 Vcc0.58 Vcc0.54 120 Vcc0.50 Vcc1.15 3.3 1.4
V V ns ns V V ps V V
IOH = 8 mA IOL = 4 mA 18 pF load 18 pF load Note 2 Note 2 Note 2 Note 3 Note 3
18
TRF
ps
Note 3
: Voltages are with respect to ground unless otherwise stated. :Typical figures are for design aid only: not guaranteed and not subject to production testing. Note: Supply voltage and operating temperature are as per Recommended Operating Conditions Note 1: The ILVPECL current is determined by termination network connected to LVPECL outputs. More than 25% of this current flows outside the chip and it does not contribute to the internal power dissipation. Note 2: Note 3: LVPECL outputs terminated with ZT = 50 resistors biased to VCC -2V (see Figure 6) CML outputs terminated with ZT = 50 resistors connected to low impedance DC bias voltage source (see Figure 7)
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AC Electrical Characteristics - Output Timing Parameters Measurement Voltage Levels Characteristics 1 Threshold Voltage Sym VT-CMOS VT-LVPECL VT-CML VHM VLM CMOS 0.5VDD LVPECL 0.5VOD_LVPECL CML
Data Sheet
Units V
0.5VOD_CML
2 3
Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low
0.7VDD 0.3VDD
0.8VOD_LVPECL 0.2VOD_LVPECL
0.8VOD_CML 0.2VOD_CML
V V
Timing Reference Points
All Signals tIF, tOF tIR, t OR
V HM VT V LM
Figure 12 - Output Timing Parameter Measurement Voltage Levels AC Electrical Characteristics - C19i Input to C19o and C77o Output Timing Characteristics 1 2 C19i to C19o delay C19i to C77oA delay Sym. tC19D tC77D Min. Typ. 6.7 -4 Max. Units ns ns Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i (19.44 MHz) C19o (19.44 MHz) t C77D C77oA (77.76 MHz) tC19D
V T-CMOS
V T-CMOS
V T-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 13 - C19i Input to C19o and C77o Output Timing
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AC Electrical Characteristics - C19i Input to OC-CLKo Output Delay Timing (CML) Characteristics 1 2 3 4 C19i to OC-CLKo(19) delay C19i to OC-CLKo(38) delay C19i to OC-CLKo(77) delay C19i to OC-CLKo(155) delay Sym. tOC-CLK19D tOC-CLK38D tOC-CLK77D tOC-CLK155D Min. Typ. 3.2 3.0 2.7 2.4 Max. Units ns ns ns ns
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i (19.44 MHz) tOC-CLK19D OC-CLKo(19) (19.44 MHz) tOC-CLK38D OC-CLKo(38) (38.88 MHz) tOC-CLK77D OC-CLKo(77) (77.76 MHz) tOC-CLK155D OC-CLKo(155) (155.52 MHz)
V T-CMOS
V T-CML
V T-CML
V T-CML
V T-CML
Note: All output clocks have nominal 50% duty cycle.
Figure 14 - C19i Input to OC-CLKo Output Timing
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AC Electrical Characteristics- C77 Clocks Output Timing Characteristics 1 2 3 C77oA to C77oB C77oA to C77oC C77oA to C77oD Sym. tC77D-AB tC77D-AC tC77D-AD Min. Typ. 100 100 100 Max. Units ps ps ps
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
C77oA t C77D-AB C77oB
V T-LVPECL
V T-LVPECL t C77D-AC
C77oC
V T-LVPECL
tC77D-AD C77oD V T-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 15 - C77oB, C77oC, C77oD Outputs Timing
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Performance Characteristics - Functional- (VCC = 3.3V 10%; TA = -40 to 85C) Characteristics 1 2 Pull-in range Lock Time Min. 1000 300 Max. Units ppm ms Notes
Data Sheet
Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance - (VCC = 3.3V 10%; TA = 40 to 85C)
GR-253-CORE Jitter Generation Requirements Interface (Category II) 1 OC-48 STS-48 OC-12 STS-12 Jitter Measurement Filter 12 kHz - 20 MHz Limit in UI 0.1 UIpp 0.01UIRMS 0.1 UIpp 12 kHz - 5 MHz 0.01UIRMS
ZL30406 Jitter Generation Performance Equivalent limit in time domain 40.2 4.02 161 16.1 Typ. 1.3 0.7 Max. 16.9 2.1 9.0 1.3
Units psP-P psRMS psP-P psRMS
2
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
Performance Characteristics: Output Jitter Generation - ETSI EN 300 462-7-1 conformance - (VCC = 3.3V 10%;
TA = -40 to 85C)
EN 300 462-7-1 Jitter Generation Requirements Jitter Measurement Filter 1 MHz to 20 MHz Limit in UI 0.1 UIpp 0.5UIpp 5 kHz to 20 MHz 2 STM-4 250 kHz to 5 MHz 0.1 UIpp 0.5 UIpp 1 kHz to 5 MHz -
ZL30406 Jitter Generation Performance Equivalent limit in time domain 40.2 201 161 804 Typ. 1.0 1.3 0.46 2.4 Max. 12.6 1.5 17.1 2.2 5.8 0.9 29.8 3.2
Interface 1 STM-16
Units psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
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Data Sheet
- (VCC = 3.3V
Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2)
10%; TA = -40 to 85C)
G.813 Jitter Generation Requirements Jitter Measurement Filter Option 1 1 STM-16 1 MHz to 20 MHz 0.1 UIpp 0.5 UIpp 5 kHz to 20 MHz 2 STM-4 250 kHz to 5 MHz 0.1 UIpp 0.5 UIpp 1 kHz to 5 MHz Option 2 3 STM-16 12 kHz - 20 MHz 4 STM-4 12 kHz - 5 MHz 0.1 UIpp 0.1 UIpp Limit in UI
ZL30406 Jitter Generation Performance
Equivalent limit in time domain
Interface
Typ.
Max.
Units
40.2 201 161 804 -
1.0 1.3 0.46 2.4
12.6 1.5 17.1 2.2 5.8 0.9 29.8 3.2
psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS
40.2 161 -
1.3 0.7
16.9 2.1 9.0 1.3
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
19
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c Zarlink Semiconductor 2005 All rights reserved.
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